264 search results - page 52 / 53 » A Time Predictable Instruction Cache for a Java Processor |
VEE
2005
ACM
13 years 11 months ago
2005
ACM
Virtual machines (VMs) are commonly used to distribute programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the desi...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
VEE
2005
ACM
13 years 11 months ago
2005
ACM
Modern transactional response-time sensitive applications have run into practical limits on the size of garbage collected heaps. The heap can only grow until GC pauses exceed the ...
PLDI
2010
ACM
13 years 10 months ago
2010
ACM
Multithreaded programs are notoriously prone to race conditions, a problem exacerbated by the widespread adoption of multi-core processors with complex memory models and cache coh...