8 search results - page 1 / 2 » A Two-level Simultaneous Test Data and Time Reduction Techni... |
JISE
2008
13 years 5 months ago
2008
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mech...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...