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» A VHDL Error Simulator for Functional Test Generation
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DATE
2000
IEEE
139views Hardware» more  DATE 2000»
9 years 2 months ago
A VHDL Error Simulator for Functional Test Generation
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
Alessandro Fin, Franco Fummi
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
9 years 1 months ago
Quality considerations in delay fault testing
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
Alicja Pierzynska, Slawomir Pilarski
EUROGP
2001
Springer
124views Optimization» more  EUROGP 2001»
9 years 2 months ago
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
An evolutionary algorithm is used to design a finite impulse response digital filter with reduced power consumption. The proposed design approach combines genetic optimization an...
Massimiliano Erba, Roberto Rossi, Valentino Libera...
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
9 years 3 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
VLSI
2007
Springer
9 years 4 months ago
Impact of hardware emulation on the verification quality improvement
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
Youssef Serrestou, Vincent Beroulle, Chantal Robac...
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