5 search results - page 1 / 1 » A case for bufferless routing in on-chip networks |
TC
2008
13 years 4 months ago
2008
On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of irregular meshes is an im...
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
DSD
2006
IEEE
13 years 10 months ago
2006
IEEE
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
SPAA
1999
ACM
13 years 9 months ago
1999
ACM
The time-constrained packet routing problem is to schedule a set of packets to be transmitted through a multinode network, where every packet has a source and a destination (as in ...