12 search results - page 1 / 3 » A comparison of three verification techniques: directed test... |
DAC
2002
ACM
14 years 5 months ago
2002
ACM
This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...
SIGSOFT
2006
ACM
14 years 5 months ago
2006
ACM
We consider the problem if a given program satisfies a specified safety property. Interesting programs have infinite state spaces, with inputs ranging over infinite domains, and f...
TCAD
2010
12 years 11 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
VLSID
2010
IEEE
13 years 2 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...