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ISSS
1997
IEEE
83views Hardware» more  ISSS 1997»
13 years 9 months ago
A Scheduling and Pipelining Algorithm for Hardware/Software Systems
Given a hardware/software partitioned specification and an allocation (number and type) of processors, we present an algorithm to (1) map each of the software behaviors (or tasks...
Smita Bakshi, Daniel Gajski
ICDE
2009
IEEE
150views Database» more  ICDE 2009»
14 years 6 months ago
Oracle Streams: A High Performance Implementation for Near Real Time Asynchronous Replication
We present the architectural design and recent performance optimizations of a state of the art commercial database replication technology provided in Oracle Streams. The underlying...
Lik Wong, Nimar S. Arora, Lei Gao, Thuvan Hoang, J...
ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
13 years 10 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
EURODAC
1994
IEEE
128views VHDL» more  EURODAC 1994»
13 years 9 months ago
A component selection algorithm for high-performance pipelines
The use of a realistic component library with multiple implementations of operators, results in cost ef cient designs; slow components can then be used on non-critical paths and t...
Smita Bakshi, Daniel D. Gajski
SIAMSC
2011
140views more  SIAMSC 2011»
12 years 7 months ago
A Fast Parallel Algorithm for Selected Inversion of Structured Sparse Matrices with Application to 2D Electronic Structure Calcu
Abstract. An efficient parallel algorithm is presented and tested for computing selected components of H−1 where H has the structure of a Hamiltonian matrix of two-dimensional la...
Lin Lin, Chao Yang, Jianfeng Lu, Lexing Ying, Wein...