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» A decoupled KILO-instruction processor
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PACS
2004
Springer
112views Hardware» more  PACS 2004»
13 years 11 months ago
Low-Overhead Core Swapping for Thermal Management
Technology scaling trends and the limitations of packaging and cooling have intensified the need for thermally efficient architectures and architecture-level temperature managemen...
Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita...
CASES
2006
ACM
13 years 12 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
13 years 11 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
PLDI
2009
ACM
14 years 6 months ago
SoftBound: highly compatible and complete spatial memory safety for c
The serious bugs and security vulnerabilities facilitated by C/C++'s lack of bounds checking are well known, yet C and C++ remain in widespread use. Unfortunately, C's a...
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Mar...
HPCA
2005
IEEE
14 years 6 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...