29 search results - page 3 / 6 » A decoupling method for analysis of coupled RLC interconnect... |
GLVLSI
2006
IEEE
14 years 6 days ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
Most existing buffering algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches...
ISCAS
2006
IEEE
14 years 5 days ago
2006
IEEE
—With the development of IC technology, it becomes urgent to investigate model reduction method for interconnects with process variations. In this paper, a one-shot projection al...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
Modeling on-chip inductive effects for interconnects of multigigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large num...
CDC
2009
IEEE
13 years 11 months ago
2009
IEEE
— We propose a compositional stability analysis methodology for verifying properties of systems that are interconnections of multiple subsystems. The proposed method assembles st...