52 search results - page 2 / 11 » A delay fault model for at-speed fault simulation and test g... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
VTS
2003
IEEE
13 years 10 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
VTS
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
ETS
2006
IEEE
13 years 10 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...