52 search results - page 4 / 11 » A delay fault model for at-speed fault simulation and test g... |
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
ATS
2003
IEEE
13 years 11 months ago
2003
IEEE
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
ATS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
ISMVL
2007
IEEE
13 years 12 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...