65 search results - page 1 / 13 » A delay model for logic synthesis of continuously-sized netw... |
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
CMSB
2006
Springer
13 years 8 months ago
2006
Springer
Based on the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach that uses timed automata. It yields a refined quali...
DAC
1994
ACM
13 years 8 months ago
1994
ACM
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
ICCAD
1992
IEEE
13 years 8 months ago
1992
IEEE
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
TCS
2008
13 years 4 months ago
2008
Starting from the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach based on timed automata. We obtain a refined ...