18 search results - page 3 / 4 » A design methodology for temperature variation insensitive l... |
DAC
2005
ACM
14 years 7 months ago
2005
ACM
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
ISVLSI
2002
IEEE
13 years 11 months ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
ISVLSI
2006
IEEE
14 years 10 days ago
2006
IEEE
We describe a new latch circuit designed to give a high performance in low voltage synchronizer applications. By increasing the latch current only during metastability, we can mor...
DATE
2008
IEEE
14 years 23 days ago
2008
IEEE
The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bioelectronic interfaces is raising a number of important issues concerning circuit arc...
ISLPED
2004
ACM
13 years 11 months ago
2004
ACM
We present a novel temperature/leakage sensor, developed for high-speed, low-power, monitoring of processors and complex VLSI chips. The innovative idea is the use of 4T SRAM cell...