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DAC
2005
ACM

Variations-aware low-power design with voltage scaling

11 years 5 months ago
Variations-aware low-power design with voltage scaling
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of process variations one should use a higher supply voltage than would otherwise be predicted to minimize the power consumption of a parallel systems. Previous analyses, which ignored WID process variations, provide a lower non-optimal supply voltage which can underestimate the energy/operation by 8.2X. We also present a novel technique to limit the effect of temperature variations in a parallel system. As temperatures increases, the scheme reduces the power increase by 43% allowing the system to remain at it's optimal supply voltage across different temperatures. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles; General Terms: Design
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2005
Where DAC
Authors Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm
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