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CICC
2011
106views more  CICC 2011»
12 years 5 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
IJCNN
2000
IEEE
13 years 10 months ago
Simulation of a Digital Neuro-Chip for Spiking Neural Networks
: Conventional hardware platforms are far from reaching real-time simulation requirements of complex spiking neural networks (SNN). Therefore we designed an accelerator board with ...
Tim Schönauer, S. Atasoy, N. Mehrtash, Heinri...
ARVLSI
1995
IEEE
132views VLSI» more  ARVLSI 1995»
13 years 9 months ago
Standard CMOS active pixel image sensors for multimedia applications
The task of image acquisition is completely dominated by CCD-based sensors fabricated on specialized process lines. These devices provide an essentially passive means of detecting...
Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid,...
ISCAS
2005
IEEE
275views Hardware» more  ISCAS 2005»
13 years 11 months ago
A low dropout, CMOS regulator with high PSR over wideband frequencies
Modern System-on-Chip (SoC) environments are swamped in high frequency noise that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupli...
Vishal Gupta, Gabriel A. Rincón-Mora
TVLSI
2010
13 years 6 days ago
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
Mohammad Taherzadeh-Sani, Anas A. Hamoui