22 search results - page 2 / 5 » A fill-unit approach to multiple instruction issue |
MICRO
1996
IEEE
13 years 9 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
ISCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
CJ
2006
13 years 5 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
CODES
2006
IEEE
13 years 9 months ago
2006
IEEE
Small area and code size are two critical design issues in most of embedded system designs. In this paper, we tackle these issues by customizing forwarding networks and instructio...