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DAC
2002
ACM
14 years 6 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
EUROMICRO
2009
IEEE
13 years 9 months ago
Synthetic Metrics for Evaluating Runtime Quality of Software Architectures with Complex Tradeoffs
Runtime quality of software, such as availability and throughput, depends on architectural factors and execution environment characteristics (e.g. CPU speed, network latency). Alth...
Anakreon Mentis, Panagiotis Katsaros, Lefteris Ang...
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
14 years 1 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
JSS
2006
104views more  JSS 2006»
13 years 5 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
CODES
2001
IEEE
13 years 8 months ago
A design framework to efficiently explore energy-delay tradeoffs
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
William Fornaciari, Donatella Sciuto, Cristina Sil...