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LCTRTS
2009
Springer
14 years 1 months ago
Live-range unsplitting for faster optimal coalescing
Register allocation is often a two-phase approach: spilling of registers to memory, followed by coalescing of registers. Extreme liverange splitting (i.e. live-range splitting aft...
Sandrine Blazy, Benoît Robillard
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 27 days ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
DAC
1997
ACM
13 years 10 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
LCTRTS
2001
Springer
13 years 10 months ago
A Dynamic Programming Approach to Optimal Integrated Code Generation
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
Christoph W. Keßler, Andrzej Bednarski
PLDI
2005
ACM
13 years 11 months ago
Demystifying on-the-fly spill code
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
Alex Aletà, Josep M. Codina, Antonio Gonz&a...