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DAC
2004
ACM
14 years 6 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
PG
2000
IEEE
13 years 9 months ago
Dynamic PDE Surfaces with Flexible and General Geometric Constraints
PDE surfaces, whose behavior is governed by Partial Differential Equations (PDEs), have demonstrated many modeling advantages in surface blending, free-form surface modeling, and ...
Haixia Du, Hong Qin
IJSM
2007
85views more  IJSM 2007»
13 years 5 months ago
Constraint Modeling for Curves and Surfaces in CAGD: a Survey
Computer-Aided Geometric Design modelers are now based on powerful mathematical curve and surface models, but there is still a considerable need for efficient tools to handle, ana...
Vincent Cheutet, Marc Daniel, Stefanie Hahmann, Ra...
ICCAD
2003
IEEE
195views Hardware» more  ICCAD 2003»
13 years 10 months ago
Vectorless Analysis of Supply Noise Induced Delay Variation
The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has...
Sanjay Pant, David Blaauw, Vladimir Zolotov, Savit...
DAC
1996
ACM
13 years 9 months ago
Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon,...