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CODES
2009
IEEE
13 years 11 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
SAC
2002
ACM
13 years 4 months ago
A mobility and traffic generation framework for modeling and simulating ad hoc communication networks
We present a generic mobility and traffic generation framework that can be incorporated into a tool for modeling and simulating large scale ad hoc networks. Three components of thi...
Christopher L. Barrett, Madhav V. Marathe, James P...
IPCCC
1999
IEEE
13 years 9 months ago
Accurately modeling speculative instruction fetching in trace-driven simulation
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challe...
R. Bhargava, L. K. John, F. Matus
APPINF
2003
13 years 6 months ago
On Reducing Entity State Update Packets in Distributed Interactive Simulations using a Hybrid Model
A key component in Distributed Interactive Simulations (DIS) is the number of data packets transmitted across the connected networks. To reduce the number of packets transmitted, ...
Declan Delaney, Tomás Ward, Séamus M...
ISPASS
2009
IEEE
13 years 11 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...