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» A low-leakage current power 180-nm CMOS SRAM
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ASPDAC
2008
ACM
120views Hardware» more  ASPDAC 2008»
13 years 6 months ago
A low-leakage current power 180-nm CMOS SRAM
Tadayoshi Enomoto, Yuki Higuchi
MTDT
2006
IEEE
154views Hardware» more  MTDT 2006»
13 years 10 months ago
SRAM Cell Current in Low Leakage Design
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, C...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
13 years 10 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
13 years 11 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
ISCAS
2007
IEEE
132views Hardware» more  ISCAS 2007»
13 years 11 months ago
High Read Stability and Low Leakage Cache Memory Cell
- Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines...
Zhiyu Liu, Volkan Kursun