45 search results - page 1 / 9 » A low-power clock frequency multiplier |
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a low-power sine-output Direct Digital Frequency Synthesizer (DDFS) realized in 0.18 µm CMOS that achieves 60 dBc spectral purity from DC to the Nyquist frequency. No ...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
- This paper describes the design of a low power
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- A 16-bit THUMB instruction set microprocessor is proposed for low cost/power in short-precision computing. It achieves 40% gate count, 51% power consumption and 160% clock freque...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
– In this paper, we introduce a high-speed and low power Phase-Frequency Detector (PFD) that is designed using modified TSPC (True Single-Phase Clock) positive edge triggered D f...