5 search results - page 1 / 1 » A nano-CMOS process variation induced read failure tolerant ... |
ISCAS
2008
IEEE
13 years 12 months ago
2008
IEEE
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
SOCC
2008
IEEE
13 years 12 months ago
2008
IEEE
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
SOCC
2008
IEEE
13 years 12 months ago
2008
IEEE
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
ATS
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell...
CASES
2009
ACM
13 years 8 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...