6 search results - page 1 / 2 » A new approach to logic synthesis of multi-output boolean fu... |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
Algorithmic logic synthesis is usually carried out in two stages, the independent stage where logic minimization is performed on the Boolean equations with no regard to physical p...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...