19 search results - page 1 / 4 » A new approach to simultaneous buffer insertion and wire siz... |
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
ISPD
1997
ACM
13 years 9 months ago
1997
ACM
In this paper, we consider the delay minimization problem of a wire by simultaneously considering bu er insertion, bu er sizing and wire sizing. We consider three versions of the ...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
We present a method for incorporating crosstalk reduction criteria into global routing under an innovative power supply architecture, while considering the constraints imposed by ...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
ISQED
2009
IEEE
13 years 11 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...