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AMCS
2010
115views Mathematics» more  AMCS 2010»
13 years 5 months ago
A new efficient and flexible algorithm for the design of testable subsystems
Stéphane Ploix, Abed Alrahim Yassine, Jean-...
FPL
2004
Springer
112views Hardware» more  FPL 2004»
13 years 10 months ago
Automating the Layout of Reconfigurable Subsystems via Template Reduction
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...
Shawn Phillips, Akshay Sharma, Scott Hauck
FCCM
2005
IEEE
131views VLSI» more  FCCM 2005»
13 years 11 months ago
Automating the Layout of Reconfigurable Subsystems Using Circuit Generators
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
Shawn Phillips, Scott Hauck
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 9 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
PIMRC
2008
IEEE
13 years 11 months ago
Algorithmic aspects of radio flexibility
—This review article explores the notion of radio flexibility, its various versions (as presented in a brief taxonomy) and its efficient instantiations under various metrics, pri...
Andreas Polydoros