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» A new pipelined adaptive DFE architecture with improved conv...
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VLSID
1996
IEEE
130views VLSI» more  VLSID 1996»
13 years 9 months ago
A systolic architecture for LMS adaptive filtering with minimal adaptation delay
Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents ...
S. Ramanathan, V. Visvanathan
ISCAS
1993
IEEE
78views Hardware» more  ISCAS 1993»
13 years 9 months ago
A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation
A fully pipelined systolic array structure for multidimensional adaptive filtering is proposed. It utilizes the wellknown McClellan Transformation (MT) to reduce the total number ...
K. J. Ray Liu, An-Yeu Wu
FPL
1997
Springer
123views Hardware» more  FPL 1997»
13 years 9 months ago
P4: A platform for FPGA implementation of protocol boosters
Protocol Boosters are functional elements, inserted anddeleted fromnetwork protocol stacks on an as-neededbasis. The Protocol Booster design methodology attempts to improve end-to-...
Ilija Hadzic, Jonathan M. Smith