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» A novel 32-bit scalable multiplier architecture
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GLVLSI
2003
IEEE
239views VLSI» more  GLVLSI 2003»
13 years 10 months ago
A novel 32-bit scalable multiplier architecture
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
Yeshwant Kolla, Yong-Bin Kim, John Carter
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
13 years 10 months ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
CGO
2010
IEEE
13 years 9 months ago
Umbra: efficient and scalable memory shadowing
Shadow value tools use metadata to track properties of application data at the granularity of individual machine instructions. These tools provide effective means of monitoring an...
Qin Zhao, Derek Bruening, Saman P. Amarasinghe
SENSYS
2006
ACM
13 years 10 months ago
The tenet architecture for tiered sensor networks
Most sensor network research and software design has been guided by an architectural principle that permits multi-node data fusion on small-form-factor, resource-poor nodes, or mo...
Omprakash Gnawali, Ki-Young Jang, Jeongyeup Paek, ...