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» A novel FPGA logic block for improved arithmetic performance
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FPGA
2006
ACM
116views FPGA» more  FPGA 2006»
13 years 9 months ago
Performance benefits of monolithically stacked 3D-FPGA
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...
Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wo...
DAC
2007
ACM
14 years 6 months ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
FPL
2009
Springer
156views Hardware» more  FPL 2009»
13 years 10 months ago
A highly scalable Restricted Boltzmann Machine FPGA implementation
Restricted Boltzmann Machines (RBMs) — the building block for newly popular Deep Belief Networks (DBNs) — are a promising new tool for machine learning practitioners. However,...
Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMaho...
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
13 years 7 months ago
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
Siew Kei Lam, Thambipillai Srikanthan
ACIVS
2006
Springer
13 years 11 months ago
Dedicated Hardware for Real-Time Computation of Second-Order Statistical Features for High Resolution Images
We present a novel dedicated hardware system for the extraction of second-order statistical features from high-resolution images. The selected features are based on gray level co-o...
Dimitris G. Bariamis, Dimitrios K. Iakovidis, Dimi...