2 search results - page 1 / 1 » A novel VLSI iterative divider architecture for fast quotien... |
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...