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» A novel approach for network on chip emulation
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SP
2010
IEEE
178views Security Privacy» more  SP 2010»
13 years 8 months ago
Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically
The computer systems security arms race between attackers and defenders has largely taken place in the domain of software systems, but as hardware complexity and design processes ...
Matthew Hicks, Murph Finnicum, Samuel T. King, Mil...
ARC
2009
Springer
175views Hardware» more  ARC 2009»
13 years 11 months ago
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve comput...
Brendan P. Glackin, Jim Harkin, T. Martin McGinnit...
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
14 years 5 months ago
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
Sanjeev Patel
NOCS
2008
IEEE
13 years 11 months ago
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
Abstract— In this paper, we discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach i...
Zheng Shi, Alan Burns
DATE
2004
IEEE
116views Hardware» more  DATE 2004»
13 years 8 months ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He