9 search results - page 1 / 2 » A novel dimension reduction technique for the capacitance ex... |
ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
In this paper, we present a new capacitance extraction method named Dimension Reduction Technique (DRT) for 3D VLSI interconnects. The DRT converts a complex 3D problem into a ser...
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
DAC
1998
ACM
14 years 5 months ago
1998
ACM
As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate threedimensional interconnect models. In this paper, we describe...
GLVLSI
2009
IEEE
13 years 2 months ago
2009
IEEE
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
In this article we address efficiency issues in implementation of Monte Carlo algorithm for 3D capacitance extraction. Error bounds in statistical capacitance estimation are discus...