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» A novel framework for multilevel full-chip gridless routing
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TCAD
2008
119views more  TCAD 2008»
13 years 5 months ago
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
14 years 2 months ago
Multilevel Approach to Full-Chip Gridless Routing
Jason Cong, Jie Fang, Yan Zhang VI
ASPDAC
2006
ACM
120views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A novel framework for multilevel full-chip gridless routing
— Due to its great flexibility, gridless routing is desirable for nanometer circuit designs that use variable wire widths and spacings. Nevertheless, it is much more difficult ...
Tai-Chen Chen, Yao-Wen Chang, Shyh-Chang Lin
DATE
2004
IEEE
116views Hardware» more  DATE 2004»
13 years 9 months ago
Full-Chip Multilevel Routing for Power and Signal Integrity
Conventional physical design flow separates the design of power network and signal network. Such a separated approach results in slow design convergence for wire-limited deep sub-...
Jinjun Xiong, Lei He
DAC
2006
ACM
14 years 6 months ago
Novel full-chip gridless routing considering double-via insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highl...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...