20 search results - page 1 / 4 » A novel methodology for transistor-level power estimation |
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
ISLPED
1996
ACM
13 years 9 months ago
1996
ACM
Transistlw-level power simulators, which are more accurate than logic-level power estimators, have been popularly used to estimate the power dissipation of CMOS circuits. In thisp...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...