26 search results - page 1 / 6 » A novel scan architecture for power-efficient, rapid test |
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
ICCD
2003
IEEE
13 years 10 months ago
2003
IEEE
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...