4 search results - page 1 / 1 » A novel ultra-fast heuristic for VLSI CAD steiner trees |
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
In dense integrated circuit designs, management of routing congestion is essential; an over congested design may be unroutable. Many factors influence congestion: placement, rout...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...