44 search results - page 1 / 9 » A reuse scenario for the VHDL-based hardware design flow |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Market reductions. The system design flow provides for codesign of (embedded) driv...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper describes ongoing research in the field of quantitative productivity measurement in IC Design and simulation of different scenarios as decision support. Five topics out...
ICALT
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper describes an approach for modeling and implementing a collaborative learning situation, which is part of a real lifelong learning scenario in astronomy. We adopt and sl...