19 search results - page 1 / 4 » A robust detailed placement for mixed-size IC designs |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
— The rapid increase in IC design complexity and wide-spread use of intellectual-property (IP) blocks have made the so-called mixed-size placement a very important topic in recen...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
In this paper, we present a new multi-packing tree (MP-tree) representation for macro placement to handle mixed-size designs. Based on binary trees, the MP-tree is very efficient,...
TCAD
2008
13 years 4 months ago
2008
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...
ICS
2011
Tsinghua U.
12 years 8 months ago
2011
Tsinghua U.
Phase-Change Memory (PCM) technology has received substantial attention recently. Because PCM is byte-addressable and exhibits access times in the nanosecond range, it can be used...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...