30 search results - page 1 / 6 » A routing approach to reduce glitches in low power FPGAs |
ISPD
2009
ACM
13 years 11 months ago
2009
ACM
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
TVLSI
2008
13 years 4 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
ASAP
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...