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SLIP
2009
ACM
14 years 9 days ago
A pre-placement net length estimation technique for mixed-size circuits
An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimatio...
Bahareh Fathi, Laleh Behjat, Logan M. Rakai
DAC
2002
ACM
14 years 6 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
DAC
2007
ACM
14 years 6 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar
NIPS
2000
13 years 7 months ago
A Silicon Primitive for Competitive Learning
Competitive learning is a technique for training classification and clustering networks. We have designed and fabricated an 11transistor primitive, that we term an automaximizing ...
David Hsu, Miguel Figueroa, Chris Diorio
ISPD
2007
ACM
151views Hardware» more  ISPD 2007»
13 years 7 months ago
Pattern sensitive placement for manufacturability
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
Shiyan Hu, Jiang Hu