7 search results - page 1 / 2 » A symbolic algorithm for low-power sequential synthesis |
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Different logic synthesis tasks have been formulated as input encoding problems but restricted to use a minimum number of binary variables. This paper presents an original column ...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
The core computation in BDD-based symbolic synthesis and verification is forming the image and pre-image of sets of states under the transition relation characterizing the sequen...