12 search results - page 2 / 3 » A universal technique for fast and flexible instruction-set ... |
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
WSC
1997
13 years 6 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
13 years 4 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
COMPUTER
2002
13 years 4 months ago
2002
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...