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RTCSA
2007
IEEE
13 years 11 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
IWMM
2011
Springer
206views Hardware» more  IWMM 2011»
12 years 8 months ago
A comprehensive evaluation of object scanning techniques
At the heart of all garbage collectors lies the process of identifying and processing reference fields within an object. Despite its key role, and evidence of many different impl...
Robin Garner, Stephen M. Blackburn, Daniel Frampto...
TECS
2008
122views more  TECS 2008»
13 years 5 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
CASES
2008
ACM
13 years 7 months ago
Reducing pressure in bounded DBT code caches
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
José Baiocchi, Bruce R. Childers, Jack W. D...
DATE
2009
IEEE
140views Hardware» more  DATE 2009»
13 years 11 months ago
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
With the relentless scaling of semiconductor technology, the lifetime reliability of embedded multiprocessor platforms has become one of the major concerns for the industry. If th...
Lin Huang, Feng Yuan, Qiang Xu