Sciweavers

47 search results - page 3 / 10
» Accelerated costas array enumeration using FPGAs
Sort
View
ARC
2010
Springer
188views Hardware» more  ARC 2010»
14 years 5 days ago
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs
Dot-products are one of the essential and recurrent building blocks in scientific computing, and often take-up a large proportion of the scientific acceleration circuitry. The ac...
Antonio Roldao Lopes, George A. Constantinides
IPPS
1998
IEEE
13 years 9 months ago
Implementing Parallelism in Random Discrete Event-Driven Simulation
Abstract. The inherently sequential nature of random discrete eventdriven simulation has made parallel and distributed processing di cult. This paper presents a method of applying ...
Marc Bumble, Lee D. Coraor
FPL
2009
Springer
132views Hardware» more  FPL 2009»
13 years 9 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
ICDM
2010
IEEE
276views Data Mining» more  ICDM 2010»
13 years 3 months ago
Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs
Many time series data mining problems require subsequence similarity search as a subroutine. While this can be performed with any distance measure, and dozens of distance measures ...
Doruk Sart, Abdullah Mueen, Walid A. Najjar, Eamon...
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
13 years 11 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...