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    » Activity-driven clock design for low power circuits
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    ICCAD
    1995
    IEEE
    129views Hardware» more  ICCAD 1995»
    Activity-driven clock design for low power circuits
    13 years 8 months ago
    Activity-driven clock design for low power circuits
    Download  www.cs.utah.edu
    In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
    Gustavo E. Téllez, Amir H. Farrahi, Majid S...
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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    13 years 7 months ago
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    Download  dropzone.tamu.edu
    Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
    Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
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    ISLPED
    2000
    ACM
    92views Hardware» more  ISLPED 2000»
    Low power sequential circuit design by using priority encoding and clock gating
    13 years 8 months ago
    Low power sequential circuit design by using priority encoding and clock gating
    Download  atrak.usc.edu
    This paper presents a state assignment technique called priority encoding which uses multi-code assignment plus clock gating to reduce power dissipation in sequential circuits. Th...
    Xunwei Wu, Massoud Pedram
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    TCAD
    2011
    231views Software Engineering» more  TCAD 2011»
    Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
    12 years 12 months ago
    Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
    Download  www.gtcad.gatech.edu
    —Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
    Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
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    ISLPED
    1995
    ACM
    122views Hardware» more  ISLPED 1995»
    A multiple clocking scheme for low power RTL design
    13 years 8 months ago
    A multiple clocking scheme for low power RTL design
    Download  www.cecs.uci.edu
    This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
    Christos A. Papachristou, Mark Spining, Mehrdad No...
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