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» Adaptive Diagnostic Pattern Generation for Scan Chains
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VTS
1997
IEEE
133views Hardware» more  VTS 1997»
13 years 9 months ago
ATPG for scan chain latches and flip-flops
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
Samy Makar, Edward J. McCluskey
ATS
2009
IEEE
135views Hardware» more  ATS 2009»
14 years 4 days ago
On Scan Chain Diagnosis for Intermittent Faults
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, E...
ET
2000
73views more  ET 2000»
13 years 5 months ago
Deterministic BIST with Partial Scan
An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum num...
Gundolf Kiefer, Hans-Joachim Wunderlich
DAC
1997
ACM
13 years 9 months ago
STARBIST: Scan Autocorrelated Random Pattern Generation
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, M...
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 5 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...