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» Adaptive Techniques for Improving Delay Fault Diagnosis
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TVLSI
2008
164views more  TVLSI 2008»
13 years 5 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
13 years 11 months ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 7 months ago
Variability-driven module selection with joint design time optimization and post-silicon tuning
Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection t...
Feng Wang 0004, Xiaoxia Wu, Yuan Xie
CSCW
2004
ACM
13 years 11 months ago
High-performance telepointers
Although telepointers are valuable for supporting real-time collaboration, they are rarely seen in commercial groupware applications that run on the Internet. One reason for their...
Jeff Dyck, Carl Gutwin, Sriram Subramanian, Chris ...
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 5 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri