7 search results - page 1 / 2 » Adaptive techniques for leakage power management in L2 cache... |
ICCD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
CASES
2008
ACM
13 years 6 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
CGO
2005
IEEE
13 years 10 months ago
2005
IEEE
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...