25 search results - page 2 / 5 » Address Bus Encoding Techniques for System-Level Power Optim... |
CODES
2004
IEEE
13 years 9 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
CASES
2003
ACM
13 years 10 months ago
2003
ACM
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
TVLSI
2002
13 years 5 months ago
2002
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...