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ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
14 years 2 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
JSW
2008
202views more  JSW 2008»
13 years 5 months ago
Change Prediction in Object-Oriented Software Systems: A Probabilistic Approach
An estimation of change-proneness of parts of a software system is an active topic in the area of software engineering. Such estimates can be used to predict changes to different c...
Ali R. Sharafat, Ladan Tahvildari
LCTRTS
2010
Springer
14 years 9 days ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
CF
2010
ACM
13 years 10 months ago
Load balancing using dynamic cache allocation
Supercomputers need a huge budget to be built and maintained. To maximize the usage of their resources, application developers spend time to optimize the code of the parallel appl...
Miquel Moretó, Francisco J. Cazorla, Rizos ...
DAC
2005
ACM
14 years 6 months ago
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Sorin Manolache, Petru Eles, Zebo Peng