104 search results - page 1 / 21 » Addressable test ports an approach to testing embedded cores |
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
DFT
2009
IEEE
14 years 22 hour ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
CSREAESA
2009
13 years 6 months ago
2009
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a progr...
DATE
2008
IEEE
2008
IEEE
State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores
13 years 7 months ago
1 We present a new type of Linear Feedback Shift Registers, State Skip LFSRs. State Skip LFSRs are normal LFSRs with the addition of a small linear circuit, the State Skip circuit,...